View MT49H32M18FM-18IT_3898371.PDF datasheet online --- IC-ON-LINE

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?products and specifications discussed here in are for evaluation and re ference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii features advance ? pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_1.fm - rev. b 1/06 en 1 ?2005 micron technology, inc. all rights reserved. 576mb cio reduced latency (rldram ? ii) mt49h16m36 mt49h32m18 mt49h64m9 for the latest data sheet, refer to mi cron?s web site: www.micron.com/rldram features ? 533 mhz ddr operation (1,067 mb/s/pin data rate) ? organization 16 meg x 36, 32 meg x 18, and 64 meg x 9 8 banks ? cyclic bank switching for maximum bandwidth ? reduced cycle time (15ns at 533 mhz) ? nonmultiplexed addresses (address multiplexing option available) ? sram-type interface ? programmable read latency (rl), row cycle time, and burst sequence length ? balanced read and write latencies in order to optimize data bus utilization ? data mask for write commands ? differential input clocks (ck, ck#) ? differential input data clocks (dkx, dkx#) ? on-chip dll generates ck edge-aligned data and output data clock signals ? data valid signal (qvld) ? 32ms refresh (16k refresh for each bank; 64k refresh command must be issued in total each 32ms) ? 144-ball bga package ? hstl i/o (1.5v or 1.8v nominal) ?25 ?60 matched impedance outputs ? 2.5v v ext , 1.8v v dd , 1.5v or 1.8v v dd q i/o ? on-die termination (odt) r tt table 1: valid part numbers part number description mt49h16m36fm-xx 16 meg x 36 rldram ii mt49h32m18fm-xx 32 meg x 18 rldram ii mt49h64m9fm-xx 64 meg x 9 rldram ii figure 1: 144-ball bga notes: 1. contact micron for availability of lead-free products. options marking ? clock cycle timing 1.875ns @ t rc = 15 2.5ns @ t rc = 15 2.5ns @ t rc = 17.5 2.5ns @ t rc = 20 3.3ns @ t rc = 16.7 3.3ns @ t rc = 20 -18 -25e -25z -25 -33e -33 ? configuration 16 meg x 36 32 meg x 18 64 meg x 9 mt49h16m36 mt49h32m18 mt49h64m9 ? operating temperature range commercial 0 to +95c industrial t c = -40c to +95c t a = -40c to +85c) none it ?package 144-ball bga (11mm x 18.5mm, lead-free) fm bm 1
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36toc.fm - rev. b 1/06 en 2 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii table of contents advance table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ball assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 programmable impedance output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 clock considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 mode register set command (mrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 write basic information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 read basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 auto refresh command (aref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 on-die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 operation with multiplexed addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 refresh command in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ieee 1149.1 serial boundary scan (jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 disabling the jtag feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 test mode select (tms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 test data-in (tdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 test data-out (tdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 performing a tap reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 tap registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 identification (id) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 tap instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 high-z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 reserved for future use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36lof.fm - rev. b 1/06 en 3 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii list of figures advance list of figures figure 1: 144-ball bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: 8 meg x 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: clock/input data clock command/ad dress timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 4: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 5: clock input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 6: mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 7: mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 8: mode register bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 9: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10: basic write burst/dm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 11: write burst basic sequence: bl = 2, rl = 4, wl = 5, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12: write burst basic sequence: bl = 4, rl = 4, wl = 5, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 13: write followed by read: bl = 2, rl = 4, wl = 5, conf iguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 14: write followed by read: bl = 4, rl = 4, wl = 5, conf iguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16: basic read burst timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17: read burst: bl = 2, rl = 4, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 18: read burst: bl = 4, rl = 4, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: read followed by write, bl = 2, rl = 4, wl = 5, co nfiguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: read followed by write, bl = 4, rl = 4, wl = 5, co nfiguration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 21: auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: auto refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 23: on-die termination-equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 24: read burst with odt: bl = 2, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 25: read nop read with odt: bl = 2, configuration 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 26: read nop nop read with odt: bl = 2, configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 27: read followed by write with odt: bl = 2, configurat ion 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 28: write followed by read with odt: bl = 2, configurat ion 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 29: command description in multiplexed address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 30: mode register set command in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 31: power-up sequence in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 32: burst refresh operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 33: write burst basic sequence: bl = 4, with mult iplexed addresses, configuration 1, wl = 6 . . . . . .35 figure 34: read burst basic se quence: bl = 4, with multiplexed addresses, configuration 1, rl = 5. . . . . . . .35 figure 35: tap controller state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 36: tap controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 37: tap timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 38: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 39: output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 40: input waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 41: 144-ball bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36lot.fm - rev. b 1/06 en 4 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii list of tables advance list of tables table 1: valid part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: 8 meg x 36 ball assignment (top view) 144-ball bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3: 16 meg x 18 ball assignment (top view) 144-ball bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: 32 meg x 9 ball assignment (top vi ew) 144-ball bga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 5: ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 7: command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 8: description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 9: ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 10: clock input operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 11: rldram configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 13: address mapping in multiplexed address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 14: configuration table in multiplexed address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 15: tap ac electrical char acteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 16: tap ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 17: tap dc electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 18: identification register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 19: scan register sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 20: instruction codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 21: boundary scan (exit) order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 22: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 23: ac electrical characteristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 24: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 25: i dd operating conditions and maximum limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 5 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii general description advance general description the micron ? 576mb reduced latency dram (rldram ? ) ii is a high-speed memory device designed for high bandwidth communication data storage?telecommunica- tions, networking, and cache applications, etc. the chip?s 8-bank architecture is opti- mized for high speed and achieves a peak bandwidth of 38.4 gb/s, using a 36-bit interface and a maximum sy stem clock of 533 mhz. the double data rate (ddr) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the i/o pins. output data is referenced to the free-running output data clock. commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is r egistered at both positive and negative edges of the input data clock(s). read and write accesses to the rldram ar e burst-oriented. the burst length is pro- grammable from 2, 4, or 8 by setting the mode register. the device is supplied with 2.5v and 1.8v for the core and 1.5v or 1.8v for the output drivers. bank-scheduled refresh is supported with row address generated internally. a standard bga 144-ball package is used to enable ultra high-speed data transfer rates and a simple upgrade path from former products.
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 6 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii functional block diagram advance functional block diagram figure 2: 16 meg x 36 notes: 1. when the bl = 4 setting is used, a19 is a ?don?t care.? when the bl = 8 setting is used, both a18 and a19 become ?don?t care.? a0?a19 1 , b0, b1, b2 c olumn a dd ress buffer c olumn a dd ress c ounter refresh c ounter row de c o d er memory array bank 1 c olumn de c o d er s ense amp an d data bus row a dd ress buffer row de c o d er memory array bank 0 c olumn de c o d er s ense amp an d data bus row de c o d er memory array bank 2 c olumn de c o d er s ense amp an d data bus row de c o d er memory array bank 3 c olumn de c o d er s ense amp an d data bus row de c o d er memory array bank 5 c olumn de c o d er s ense amp an d data bus row de c o d er memory array bank 4 c olumn de c o d er s ense amp an d data bus row de c o d er memory array bank 6 c olumn de c o d er s ense amp an d data bus row de c o d er memory array bank 7 c olumn de c o d er c k c k# dk[1:0] dk#[1:0] we# cs # ref# dm v ref s ense amp an d data bus output data vali d qvld output data c lo c k qk[1:0], qk#[1:0] input buffers output buffers c ontrol lo g i c an d timin g generator dq0?dq35
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 7 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii ball assignment and description advance ball assignment and description table 2: 16 meg x 36 ball assignment (top view) 144-ball bga notes: 1. reserved for future use. th is may optionally be connected to g nd. 2. reserved for future use. this signal is inte rnally connected and has parasitic characteristics of an address input signal. this may optionally be connected to g nd. 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dq8 dq9 v ss qv ss q dq1 dq0 v dd c v tt dq10 dq11 v dd qv dd q dq3 dq2 v tt d (a22) 1 dq12 dq13 v ss qv ss q qk0# qk0 v ss e (a21) 2 dq14 dq15 v dd qv dd q dq5 dq4 (a20) 2 f a5 dq16 dq17 v ss qv ss q dq7 dq6 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss l a4 a3 j dk0 dk0# v dd v dd v dd v dd lb0 ck k dk1 dk1# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dq24 dq25 v ss qv ss q dq35 dq34 a19 p a15 dq22 dq23 v dd qv dd q dq33 dq32 dm r v ss qk1 qk1# v ss qv ss q dq31 dq30 v ss t v tt dq20 dq21 v dd qv dd q dq29 dq28 v tt u v dd dq18 dq19 v ss qv ss q dq27 dq26 v dd v v ref zq v ext v ss v ss v ext tdo tdi
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 8 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii ball assignment and description advance table 3: 32 meg x 18 ball assignment (top view) 144-ball bga notes: 1. reserved for future use. th is may optionally be connected to g nd. 2. reserved for future use. this signal is inte rnally connected and has parasitic characteristics of an address input signal. this may optionally be connected to g nd 3. no function. this signal is internally connec ted and has parasitic char acteristics of a clock input signal. 4. do not use. this signal is internally connec ted and has parasitic characteristics of an i/o. this may optionally be connected to g nd. 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dnu 4 dq4 v ss qv ss q dq0 dnu 4 v dd c v tt dnu 4 dq5 v dd qv dd q dq1 dnu 4 v tt d (a22) 1 dnu 4 dq6 v ss qv ss q qk0# qk0 v ss e (a21) 2 dnu 4 dq7 v dd qv dd q dq2 dnu 4 a20 f a5 dnu 4 dq8 v ss qv ss q dq3 dnu 4 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss l a4 a3 j nf 3 nf 3 v dd v dd v dd v dd lb0 ck k dk dk# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dnu 4 dq14 v ss qv ss q dq9 dnu 4 a19 p a15 dnu 4 dq15 v dd qv dd q dq10 dnu 4 dm r v ss qk1 qk1# v ss qv ss q dq11 dnu 4 v ss t v tt dnu 4 dq16 v dd qv dd q dq12 dnu 4 v tt u v dd dnu 4 dq17 v ss qv ss q dq13 dnu 4 v dd v v ref zq v ext v ss v ss v ext tdo tdi
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 9 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii ball assignment and description advance table 4: 64 meg x 9 ball assignment (top view) 144-ball bga notes: 1. reserved for future use. this signal is not connected. 2. no function. this signal is internally connec ted and has parasitic char acteristics of a clock input signal. 3. do not use. this signal is internally connec ted and has parasitic characteristics of an i/o. this may optionally be connected to g nd. 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dnu 3 dnu 3 v ss qv ss q dq0 dnu 3 v dd c v tt dnu 3 dnu 3 v dd qv dd q dq1 dnu 3 v tt d (a22) 1 dnu 3 dnu 3 v ss qv ss q qk0# qk0 v ss e a21 dnu 3 dnu 3 v dd qv dd q dq2 dnu 3 a20 f a5 dnu 3 dnu 3 v ss qv ss q dq3 dnu 3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h b2 a9 v ss v ss v ss v ss l a4 a3 j nf 2 nf 2 v dd v dd v dd v dd lb0 ck k dk dk# v dd v dd v dd v dd b1 ck# l ref# cs# v ss v ss v ss v ss a14 a13 m we# a16 a17 v dd v dd a12 a11 a10 n a18 dnu 3 dnu 3 v ss qv ss q dq4 dnu 3 a19 p a15 dnu 3 dnu 3 v dd qv dd q dq5 dnu 3 dm r v ss dnu 3 dnu 3 v ss qv ss q dq6 dnu 3 v ss t v tt dnu 3 dnu 3 v dd qv dd q dq7 dnu 3 v tt u v dd dnu 3 dnu 3 v ss qv ss q dq8 dnu 3 v dd v v ref zq v ext v ss v ss v ext tdo tdi
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 10 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii ball assignment and description advance table 5: ball descriptions symbol type description ck, ck# input input clock: ck and ck# are differential cloc k inputs. addresses and commands are latched on the rising edge of ck. ck# is idea lly 180 degrees out of phase with ck. cs# input chip select: cs# enables the command deco der when low and disables it when hi g h. when the command decoder is disabled, ne w commands are ignored, but internal operations continue. we#, ref# input command inputs: sampled at the positive edge of ck, we#, and ref# define (together with cs#) the command to be executed. a[0:21] input address inputs: a[0:21] define the row and column addresses for read and write operations. during a mode re g ister set, the address inputs define the register settings. they are sampled at the rising edge of ck. in the x36 config uration, a[21:20] are reserved for address expansion; in the x18 configuratio n, a[21] is reserved for address expansion. these expansion addresses can be treated as address inputs, but they do not affect the operation of the device. a22 ? reserved for future use. this signal is not connected and may be connected to ground. ba[0:2] input bank address inputs: select to which in ternal bank a command is being applied. dq0?dq35 input/output data input/output: the dq si gnals form the 36-bit data bu s. during read commands, the data is referenced to both edges of qk. du ring write commands, the data is sampled at both edges of dkx. qkx, qkx# output output data clocks: qkx and qkx# are opposite polarity, output data clocks. during reads, they are free running and edge-aligned with data output from the rldram. qkx# is ideally 180 degrees out of phase with qkx. for the x36 device, qk0 and qk0# are aligned with dq0?dq17. qk1 and qk1# are aligned wi th dq18?dq35. for the x18 device, qk0 and qk0# are aligned with dq0?dq8. qk1 and qk1# are aligned with dq 9?dq17. consult the rldram ii design guide for more details. dkx, dkx# input input data clock: dkx and dkx# are the differ ential input data cloc ks. all input data is referenced to both edges of dkx. dkx# is ideally 180 degrees out of phase with dkx. for the x36 device, dq0?dq17 are referenced to dk0 and dk0#, and dq18?dq35 are referenced to dk1 and dk1#. fo r the x9 and x18 devices, all dqs are referenced to dk and dk#. dm input input data mask: the dm signal is the input mask signal for write data. input data is masked when dm is sampled hi g h, along with the write input data. dm is sampled on both edges of dk (dk1 for the x36 configuration). qvld output data valid: the qvld indicates valid output data. qvld is edge-aligned with qkx and qkx#. tms tdi input ieee 1149.1 test inputs: these balls may be left no connects if the jta g function is not used in the circuit tck input ieee 1149.1 clock input: this ball must be tied to v ss if the jta g function is no t used in the circuit. tdo output ieee 1149.1 test output: jta g output. zq input/output external impedance [25?60 ]: this signal is used to tune the device outputs to the system data bus impedance. dq output impedance is set to 0.2 rq , where rq is a resistor from this signal to ground . connecting zq to g nd invokes the minimum impedance mode. connecting zq to v dd invokes the maximum impedanc e mode. refer to figure 8 on page 19 to activate this function. v ref input input reference voltage: nominally v dd q/2. provides a reference voltage for the input buffers. v ext supply power supply: 2.5v nom inal. see table 23 on page 45 for range. v dd supply power supply: 1.8v nom inal. see table 23 on page 45 for range. v dd q supply dq power supply: nominally, 1. 5v or 1.8v. isolated on th e device for improved noise immunity. see table 23 on page 45 for range.
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 11 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii commands advance commands according to the functional signal description, the following command sequences are possible. all input states or sequences not shown are illegal or reserved. all command and address inputs must meet setup and ho ld times around the rising edge of ck. notes: 1. x = ?don?t care? h = logic hi g h l = logic low a = valid address ba = valid bank address 2. only a(17:0) are used for the mrs command. 3. see table 6. v dd l supply dll power supply: nominally, 1.8v. isolated on the device for impr oved noise immunity. see table 23 on page 45 for range. v ss supply g round. v ss q supply dq ground: isolated on the devi ce for improved noise immunity. v ss l supply dll ground: isolated on the device for improved noise immunity. v tt supply power supply: isolated termin ation supply. nominally, v dd q/2. see table 23 on page 45 for range. nf ? no function: these balls may be connected to ground. dnu ? do not use: these balls may be connected to ground. table 6: address widths at different burst lengths burst length configuration x36 x18 x9 bl = 2 19:0 20:0 21:0 bl = 4 18:0 19:0 20:0 bl = 8 17:0 18:0 19:0 ta bl e 7 : com ma nd tab le note 1 operation code cs# we# ref# a[21:0] b[2:0] notes device deselect/no operation desel/nophxxxx mrs: mode re g ister set mrslllopcodex2 read read l h h a ba 3 write write l l h a ba 3 auto refresh aref l h l x ba table 5: ball descriptions (continued) symbol type description
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 12 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii commands advance notes: 1. when the chip is deselected, internal nop commands are generated and no commands are accepted. 2. actual refresh is 32ms/16k/8 = 0.244s. 3. actual refresh is 32ms/16k = 1.95s. table 8: description of commands command description desel/nop 1 the nop command is used to perform a no operat ion to the rldram, which essentially deselects the chip. use the nop command to prevent unwanted commands from being registered during idle or wait states. operations already in progress are not affe cted. output values depend on command history. mrs the mode register is set via the address inpu ts a(17:0). see figure 8 on page 19 for further information. the mrs command can only be issued when all banks are idle and no bursts are in progress. read the read command is used to initiate a burst read access to a bank. the value on the ba(2:0) inputs selects the bank, and the address provided on inputs a(21:0) selects th e data location within the bank. write the write command is used to initiate a burst write access to a bank. the value on the ba(2:0) inputs selects the bank, and the address provided on inputs a(21:0) selects th e data location within the bank. input data appearing on the dqs is writ ten to the memory array subject to the dm input logic level appearing coincident with the data . if the dm signal is registered low, the corresponding data will be written to me mory. if the dm signal is registered hi g h, the corresponding data inputs will be ignored (i.e., th is part of the data word will not be written). aref the aref is used during no rmal operation of the rldram to refresh the memory content of a bank. the command is nonpersistent, so it must be issued each time a refres h is required. the value on the ba(2:0) inputs selects th e bank. the refresh address is generated by an internal refresh controller, effectively making each address bit a ?don?t care ? during the aref command. the rldram requires 128k cycles at an average periodic interval of 0.24s 2 (max). to improve efficiency, eight aref co mmands (one for each bank) can be po sted to the rldram at periodic intervals of 1.95s 3 .
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 13 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii commands advance notes: 1. all timing parameters are measured relative to the crossing point of ck/ck#, dk/dk# and to the crossing point with v ref of the command, address, and data signals. 2. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 3. t qkq0 is referenced to q0?q17 in x36 and q0?q8 in x18. t qkq1 is referenced to q18?q35 in x36 and q9?q17 in x18. 4. t qkq takes into account the skew between any qkx and any q. table 9: ac electrical characteristics (-13e/-25e/-25z) note 1 description symbol -18e -25e -25z units notes min max min max min max clock clock cycle time t ck, t dk 1.875 5.7 2.5 5.7 2.5 5.7 ns system frequency f ck, f dk 175 533 175 400 175 400 mhz random cycle time t rc 15 15 17.5 ns clock jitter - period t jit per -100 100 -150 150 -150 150 ps 2 clock jitter - cycle to cycle t jit cc 200 300 300 ps clock hi g h time t ckh, t dkh 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low time t ckl, t dkl 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock to input data clock t ckdk -0.3 0.3 -0.5 0.5 -0.5 0.5 ns mode register set cycle time to any command t mrsc666 t ck setup times address/command and input setup time t as/ t cs 0.3 0.4 0.4 ns data-in and data mask to dk setup time t ds 0.17 0.25 0.25 ns hold times address/command and input hold time t ah/ t ch 0.3 0.4 0.4 ns data-in and data mask to dk hold time t dh 0.17 0.25 0.25 ns data and data strobe output data clock hi g h time t qkh 0.9 1.1 0.9 1.1 0.9 1.1 t ckh output data clock low time t qkl 0.9 1.1 0.9 1.1 0.9 1.1 t ckl qk edge to clock edge skew t ckqk -0.2 0.2 -0.25 0.25 -0.25 0.25 ns qk edge to output data edge t qkq0, t qkq1 -0.12 0.12 -0.2 0.2 -0.2 0.2 ns 3 qk edge to any output data edge t qkq -0.22 0.22 -0.3 0.3 -0.3 0.3 ns 4 qk edge to qvld t qkvld -0.22 0.22 -0.3 0.3 -0.3 0.3 ns
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 14 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii commands advance notes: 1. all timing parameters are measured relative to the crossing point of ck/ck#, dk/dk# and to the crossing point with v ref of the command, address, and data signals. 2. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 3. t qkq0 is referenced to q0?q17 in x36 and q0?q8 in x18. t qkq1 is referenced to q18?q35 in x36 and q9?q17 in x18. 4. t qkq takes into account the skew between any qkx and any q. table 10: ac electrical characteristics (-25/-33z/-33) note 1 description symbol -25 -33z -33 units notes min max min max min max clock clock cycle time t ck, t dk 2.5 5.7 3.3 5.7 3.3 5.7 ns system frequency f ck, f dk 175 400 175 300 175 300 mhz random cycle time t rc 20 16.7 20 ns clock jitter - period t jit per -150 150 -200 200 -200 200 ps 2 clock jitter - cycle to cycle t jit cc 200 400 400 ps clock hi g h time t ckh, t dkh 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low time t ckl, t dkl 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock to input data clock t ckdk -0.3 1.0 -0.3 1.5 -0.3 1.5 ns mode register set cycle time to any command t mrsc666 t ck setup times address/command and input setup time t as/ t cs 0.4 0.5 0.5 ns data-in and data mask to dk setup time t ds 0.25 0.3 0.3 ns hold times address/command and input hold time t ah/ t ch 0.4 0.5 0.5 ns data-in and data mask to dk hold time t dh 0.25 0.3 0.3 ns data and data strobe output data clock hi g h time t qkh 0.9 1.1 0.9 1.1 0.9 1.1 t ckh output data clock low time t qkl 0.9 1.1 0.9 1.1 0.9 1.1 t ckl qk edge to clock edge skew t ckqk -0.25 0.25 -0.3 0.3 -0.3 0.3 ns qk edge to output data edge t qkq0, t qkq1 -0.2 0.2 -0.25 0.25 -0.25 0.25 ns 3 qk edge to any output data edge t qkq -0.3 0.3 -0.35 0.35 -0.35 0.35 ns 4 qk edge to qvld t qkvld -0.3 0.3 -0.35 0.35 -0.35 0.35 ns
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 15 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii initialization advance figure 3: clock/input data clock command/address timings initialization the rldram must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operations or permanent damage to the device. the following sequence is used for power-up: 1. apply power (v ext , v dd , v dd q, v ref , v tt ). if ck/ck# cannot be static and meet v id ( dc ) prior to the supply voltages being stable, cs# must be high. apply v dd and v ext before or at the same time as v dd q. apply v dd q before or at the same time as v ref and v tt . although there is no timing relation between v ext and v dd , the chip starts the power-up sequence only after bo th voltages are at their nominal levels. maintain all remaining balls in nop conditions. 2. maintain stable conditions for 200s (min). 3. issue three back-to-back and clock consecutive mrs commands: two dummies plus one valid mrs. it is recommended that the address lines during the dummy mrs commands are the same value as they are during the valid mrs. 4. t mrsc after the valid mrs, issue eight au to refresh commands, one on each bank and separated by 2,048 cycles. initial bank refresh order does not matter. 5. after t rc, the chip is ready for normal operation. ck# ck t ckh t ckl t ah t as t ck cmd, addr dkx# dkx t ckdk t ckdk don?t care t dkh t dkl t dk valid valid valid
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 16 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii programmable impedance output buffer advance figure 4: power-up sequence notes: 1. rfx: refresh bank x ac: any command programmable impedance output buffer the rldram ii is equipped with programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an exter- nal precision resistor (rq) is connected between the zq ball and v ss . the value of the resistor must be five times the desired impedance. for example, a 300 resistor is required for an output impedance of 60 . to ensure that output impedance is one fifth the value of rq (within 15 percent), the range of rq is 125 to 300 . output impedance updates may be required be cause, over time, variations may occur in supply voltage and temperature. the device samples the value of rq. an impedance update is transparent to the system and does not affect device operation. all data sheet timing and current specificatio ns are met during an update. clock considerations the rldram ii utilizes internal delay-lock ed loops for maximum output, data valid windows. it can be placed into a stopped-cl ock state to minimize power with a modest restart time of 1,024 cycles. table 11: clock input operating conditions notes 1?8 parameter/condition symbol min max units notes clock input voltage level; ck and ck# v in ( dc ) -0.3v dd q + 0.3 v clock input differential voltage; ck and ck# v id ( dc )0.2v dd q + 0.6 v 9 clock input differential voltage; ck and ck# v id ( ac )0.4v dd q + 0.6 v 9 clock input crossing point voltage; ck and ck# v ix ( ac )v dd q/2 - 0.15 v dd q/2 + 0.15 v 10 v ext v dd v dd q v ref ck# ck cmd 200s min t mrsc t rc 2,048 cycles min 6 2,048 cycles min mrs mrs mrs rf0 rf1 rf7 ac don?t care add v tt nop nop nop
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 17 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii clock considerations advance figure 5: clock input notes: 1. dkx and dkx# have the same requirements as ck and ck#. 2. all voltages referenced to v ss . 3. tests for ac timing, i dd , and electrical ac a nd dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device opera- tions are tested for the full voltage range specified. 4. outputs (except for i dd measurements) measured with equivalent load. 5. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is st ill referenced to v ref (or to the crossing po int for ck/ck#), and parameter specifications are te sted for the specified ac inpu t levels under normal use con- ditions. the mini mum slew rate for the input signals used to test the device is 2 v/ns in the range between v il ( ac ) and v ih ( ac ). 6. the ac and dc input level specifications are as defined in the hstl standard (i.e., the receiver will effectively switch as a result of the signal crossi ng the ac input level, and will remain in that state as long as the signal do es not ring back above [below] the dc input low [hi g h] level). 7. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross. the input reference le vel for signals other than ck/ck# is v ref . 8. ck and ck# input slew rate must be 2 v/ns ( 4 v/ns if measured differentially). 9. v id is the magnitude of the difference betwee n the input level on ck and the input level on ck#. 10. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 11. ck and ck# must cros s within this region. 12. ck and ck# must meet at least v id ( dc ) min when static and centered around v dd q/2. 13. minimum peak-to-peak swing. ck ck# v in ( dc ) max 11 12 maximum clock level minimum clock level 13 v in ( dc ) min v dd q/2 v dd q/2 + 0.15 v dd q/2 - 0.15 x x v id ( ac ) v id ( dc ) v ix ( ac ) max v ix ( ac ) min
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 18 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii mode register set command (mrs) advance mode register set command (mrs) the mode register stores the data for contro lling the operating modes of the memory. it programs the rldram configuration, burst le ngth, test mode, and i/o options. during a mrs command, the address inputs a(17:0) ar e sampled and stored in the mode regis- ter. t mrsc must be met before any command can be issued to the rldram. the mode register may be set at any time during de vice operation. however, any pending opera- tions are not guaranteed to successfully co mplete. see the rldram ii design guide for more details. figure 6: mode register set timing figure 7: mode register set note: cod: code to be loaded into the register. ck# ck cmd t mrsc mrs nop nop ac ck# ck we # ref# a(17:0) cs# cod a(20:18) ba(2:0) don?t care
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 19 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii configuration table advance figure 8: mode register bit map notes: 1. bits a(17:10) must be set to zero. 2. bl = 8 is not available for configurations 1 and 4. 3. 15% temperature variation. configuration table table 12 shows, for different operating frequencies, the different rldram configura- tions that can be programmed into the mode register. the read and write latency ( t rl and t wl) values along with the row cycle times ( t rc) are shown in clock cycles as well as in nanoseconds. the shaded areas correspond to configurations that are not allowed. notes: 1. bl = 8 is not availabl e for configurations 1 and 4. table 12: rldram configuration table (calculating t rc based off of clock frequency) example clock frequencies symbol configuration units 1 1 2 3 4 1 5 6 t rc468357cycles t rl468357cycles t wl579468cycles 533 mhz t rc 15.0 ns t rl 15.0 ns t wl 16.875 ns 400 mhz t rc 15.0 20.0 17.5 ns t rl 15.0 20.0 17.5 ns t wl 17.5 22.5 20.0 ns 300 mhz t rc 20.0 26.7 16.7 23.3 ns t rl 20.0 26.7 16.7 23.3 ns t wl 23.3 30.0 20.0 26.7 ns 200 mhz t rc 20.0 30.0 40.0 15.0 25.0 35.0 ns t rl 20.0 30.0 40.0 15.0 25.0 35.0 ns t wl 25.0 35.0 45.0 20.0 30.0 40.0 ns a2 a4 a5 a(17:10) a3 a1 a0 a 6 a7 a3 0 1 bl 4 a4 0 1 8 0 0 1 1 reserve d 1 a9 a7 0 1 a8 a2 a1 a0 10 c onfi g uration c onfi g uration rldram c onfi g uration 1 2 ( d efault) 5 6 reserve d 1 2 not vali d 2 ( d efault) dll ena b le d dll reset dll reset burst len g th burst len g th dll reset a dd ress mux a dd ress mux dll reset ( d efault) 2 3 4 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 impe d an c e mat c hin g impe d an c e mat c hin g a8 0 1 resistor external a5 0 1 nonmultiplexe d ( d efault) a dd ress multiplexe d a dd ress mux a9 0 1 ena b le d termination on-die termination disa b le d ( d efault) on-die termination unuse d 2
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 20 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii write basic information advance write basic information write accesses are initiated with a write command, as shown in figure 9. row and bank addresses are provided together with the write command. during write commands, data will be register ed at both edges of dk according to the programmed burst length (bl). a write late ncy (wl) one cycle longer than the pro- grammed read latency (rl + 1) is present, with the first valid data registered at the first rising dk edge wl cycles after the write command. any write burst may be followed by a subs equent read command. figures 13 and 14 illustrate the timing requirements for a write followed by a read for bursts of two and four, respectively. setup and hold times for incoming dq relative to the dk edges are specified as t ds and t dh. the input data is masked if the corresponding dm signal is high. the setup and hold times for data mask are also t ds and t dh. figure 9: write command note: a: address; ba: bank address. c k# c k we# ref# cs # a a(20:0) ba(2:0) ba don?t c are
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 21 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii write basic information advance figure 10: basic write burst/dm timing figure 11: write burst basic sequence: bl = 2, rl = 4, wl = 5, configuration 1 notes: 1. a/ba x : address a of bank x wr: write command d xy : data y to bank x rc: row cycle time dq dm t dh t ds d0 d1 d2 d3 dkx# dkx t dh t ds t dh t ds don?t care write latency data masked data masked ck# ck t ckdk ck# ck cmd 012345678 addr wl = 5 d d0a d1a d0b d1b d2a d2b d3a d3 wr a ba0 a ba1 a ba2 a ba3 a ba0 a ba4 a ba5 a ba6 a ba7 wr wr wr wr wr wr wr wr dk# dk rc = 4 don?t care
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 22 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii write basic information advance figure 12: write burst basic sequence: bl = 4, rl = 4, wl = 5, configuration 1 notes: 1. any free bank may be used in any given cm d. the sequence shown is only one example of a bank sequence. figure 13: write followed by read: bl = 2, rl = 4, wl = 5, configuration 1 note: rd: read qx y : data y from bank x addr a ba0 a ba1 a ba0 a ba3 a ba0 ck# ck cmd 012345678 wl = 5 d d0a d0c d0b d0d d1a d1b d1c d1 wr nop wr nop wr nop wr nop wr don?t care dk# dk rc = 4 undefined ck# ck cmd 012 34567 89 addr wl = 5 rl = 4 dq q1a q2a q1b q2b d0a d0b wr a ba0 a ba1 a ba2 nop rd rd nop nop nop nop nop nop don?t care qkx qkx# dkx# dkx qvld
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 23 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii write basic information advance figure 14: write followed by read: bl = 4, rl = 4, wl = 5, configuration 1 undefined ck# ck cmd 012 34567 89 addr wl = 5 rl = 4 dq q1a q1c q1b q1d q2a d0a d0b d0c d0d wr a ba0 a ba1 a ba2 nop nop rd nop rd nop nop nop nop qkx qkx# dkx# dkx don?t care qvld
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 24 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii read basic information advance read basic information read accesses are initiated with a read command, as shown in figure 15. row and bank addresses are provided with the read command. during read bursts, the memory device drives the read data edge-aligned with the qk signal. after a programmable re ad latency, data is available at the outputs. the data valid signal indicates that valid data will be present in the next half clock cycle. the skew between qk and the crossing point of ck is specified as t ckqk. t qkq0 is the skew between qk0 and the last valid data edge considered over all the data generated at the dq signals. t qkq1 is the skew between qk1 and the last valid data edge considered over all the data generated at the dq signals. t qkqx is derived at each qkx clock edge and is not cumulative over time. t qkq is the maximum of t qkq0 and t qkq1. after completion of a burst, assuming no other commands have been initiated, output data (dq) will go high-z. back-to-back read commands are possible, producing a con- tinuous flow of output data. the data valid window is derived from each qk transitions and is defined as: min ( t qkh, t qkl) - 2( t qkq [max]). any read burst may be followed by a subsequent write command. figures 19 and 20 illustrate the timing requirements for a read followed by a write. depending on the programmed read latency, a read-to-write delay occurs in order to prevent bus con- tention. some systems having long line lengths or severe skews may need additional idle cycles inserted. refer to the rldram ii design guide for more details. figure 15: read command ck# ck we# ref# cs# a ba a(20:0) ba(2:0) don?t care
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 25 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii read basic information advance figure 16: basic read burst timing notes: 1. minimum data valid window can be expressed as min ( t qkh, t qkl) - 2 t qkqx (max). 2. t qkq0 is referenced to dq0?dq 17 in x36 and dq0?dq8 in x18. t qkq1 is referenced to dq18?dq35 in x36 and dq9?dq17 in x18. 3. t qkq takes into account the skew between any qkx and any dq. figure 17: read burst: bl = 2, rl = 4, configuration 1 undefined t qkvld t qkvld t qkq note 1 t qkq t qkq t ckqk qvld dq ck# ck qkx qkx# t ckh t ckl t ck q0 q1 q2 q3 t qkl t qkh ck# ck cmd 012345678 addr rc = rl = 4 dq qkx qkx# q0a q1a q0b q1b q2a q2b q3a q3b q0a rd a ba0 a ba1 a ba2 a ba3 a ba0 a ba7 a ba6 a ba5 a ba4 rd rd rd rd rd rd rd rd don?t care undefined qvld
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 26 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii read basic information advance figure 18: read burst: bl = 4, rl = 4, configuration 1 figure 19: read followed by write, bl = 2, rl = 4, wl = 5, configuration 1 ck# ck cmd 012345678 addr rc = rl = 4 dq qkx qkx# q0a q0c q0b q0d q1a q1b q1c q1d q0a rd a ba0 a ba1 a ba0 a ba1 a ba3 nop rd nop rd nop rd nop rd don?t care undefined qvld q0a q0b ck# ck cmd 012345678 addr rl = 4 dq qkx qkx# d1a d1b rd a ba0 a ba1 wr wr nop nop nop nop nop nop don?t care undefined 9 a ba2 wl = 5 dkx# dkx d2a d2b qvld
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 27 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii read basic information advance figure 20: read followed by write, bl = 4, rl = 4, wl = 5, configuration 1 q0a ck# ck cmd 01234567 addr rl = 4 qkx qkx# rd a ba0 a ba1 nop wr nop nop nop nop nop don?t care wl = 5 dq d1a d1b q0c q0b q0d dkx# dkx undefined qvld
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 28 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii auto refresh command (aref) advance auto refresh command (aref) aref is used to perform a refresh cycle on one row in a specific bank. the row addresses are generated by an internal refr esh counter for each bank; external address balls are ?don?t care.? the delay between the aref command and a subsequent com- mand to the same bank must be at least t rc. within a period of 32ms ( t ref), the entire memory must be refreshed. figure 22 illus- trates an example of a continuous refresh sequence. other refresh strategies, such as burst refresh, are also possible. figure 21: auto refresh command figure 22: auto refresh cycle notes: 1. ac x : any command on bank x arf x : auto refresh bank x ac y : any command on different bank 2. t rc is configuration-dependent. refer to table 12 on page 19. ck# ck we# ref# cs# a(20:0) ba(2:0) ba don?t care ck# ck cmd t rc arf x ac y ac x ac y arf x ac y don?t care
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 29 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii on-die termination advance on-die termination on-die termination (odt) is enabled by setting a9 to ?1? during a mrs command. with odt on, all the dqs and dm are terminated to v tt with a resistance r tt . the command, address, and clock signals are not terminated. figure 23 below shows the equivalent cir- cuit of a dq receiver with odt. odts ar e dynamically switched off during read com- mands and are designed to be off prior to the rldram driving the bus. similarly, odts are designed to switch on after the rldr am has issued the last piece of data. notes: 1. all voltages referenced to v ss ( g nd). 2. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. the r tt value is measured at +70c t c . figure 23: on-die termination-equivalent circuit figure 24: read burst with odt: bl = 2, configuration 1 table 13: on-die termination dc parameters description symbol min max units notes termination voltage v tt 0.95 v ref 1.05 v ref v1, 2 on-die termination r tt 135 165 3 v tt r tt sw driver dq ck# ck cmd 012345678 addr rl = 4 dq qkx qkx# q0a q1a q0b q1b q2a q2b rd a ba0 a ba1 a ba2 rd rd nop nop nop nop nop nop don?t care undefined odt odt on qvld odt off odt on
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 30 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii on-die termination advance figure 25: read nop read with odt: bl = 2, configuration 1 figure 26: read nop nop read wi th odt: bl = 2, configuration 1 ck# ck cmd 012345678 addr rl = 4 dq qkx qkx# q0a q0b q2a q2b rd a ba0 a ba2 nop rd nop nop nop nop nop nop don?t care undefined odt odt on qvld odt on odt off odt off odt on ck# ck cmd 012345678 addr rl = 4 dq qkx qkx# q0a q0b q2a q2b rd a ba0 a ba2 nop nop rd nop nop nop nop nop don?t care undefined odt odt on qvld odt on odt off odt off odt on 9
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 31 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii on-die termination advance figure 27: read followed by write with odt: bl = 2, configuration 1 figure 28: write followed by read with odt: bl = 2, configuration 1 ck# ck cmd 012345678 addr rl = 4 dq qkx qkx# q0a q0b d1a d1b rd a ba0 a ba1 wr wr nop nop nop nop nop nop don?t care undefined odt odt on odt on odt off 9 a ba2 wl = 5 dkx# dkx d2a d2b undefined ck# ck cmd 012 34567 89 addr wl = 5 rl = 4 dq q1a q2a q1b q2b d0a d0b wr a ba0 a ba1 a ba2 nop rd rd nop nop nop nop nop nop don?t care qkx qkx# dkx# dkx odt odt on odt on odt off
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 32 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii operation with multiplexed addresses advance operation with multiplexed addresses in multiplexed address mode, the address can be provided to the rldram in two parts that are latched into the memory with two consecutive rising clock edges. this provides the advantage that a maximum of 11 address balls are required to control the rldram, reducing the number of balls on the controll er side. the data bus efficiency in continu- ous burst mode is not affected for bl = 4 and bl = 8 since at least two clocks are required to read the data out of the memory. the bank addresses are delivered to the rldram at the same time as the write command and the first address part, a x . this option is available by setting bit a5 to ?1? in the mode register. once this bit is set, the read, write, and mrs commands follow the format described in figure 29. see figure 31 on page 33 for the power-up sequence. figure 29: command description in multiplexed address mode notes: 1. the minimum setup and hold time s of the two address parts are defined t as and t ah. ck# ck we# ref# cs# ax ba a<20:0> ba<2:0> read ay ax ba write ay ax ba don?t care mrs ay
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 33 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii operation with multiplexed addresses advance figure 30: mode register set command in multiplexed address mode notes: 1. the addresses a0, a3, a4, a5, a8, and a9 mu st be set as follows in order to activate the mode register in the mu ltiplexed address mode 2. bits a(17:10) must be set to zero. 3. bl = 8 is not available for configuration 1. 4. 15% temperature variation. figure 31: power-up sequence in multiplexed address mode notes: 1. the above sequence must be respected in order to power-up the rldram in the multiplexed address mode . 2. address a5 must be set hi g h (muxed address mode setting when rldram is in normal mode of operation). 3. address a5 must be set hi g h (muxed address mode setting when rldram is already in muxed address mode). a4 a5 a4 a3 a3 a0 a8 a9 a3x 0 1 bl 4 a4x 0 1 8 0 0 1 1 a9 a9y 0 1 a8 a4y a3y a0x 10 c onfi g uration c onfi g uration rldram c onfi g uration 1 2 ( d efault) 5 6 reserve d 1 2 not vali d 2 ( d efault) dll ena b le d dll reset dll reset burst len g th burst len g th dll reset a dd ress mux a dd ress mux dll reset ( d efault) 2 3 4 10 11 01 01 00 00 1 1 0 0 1 0 1 0 11 impe d an c e mat c hin g impe d an c e mat c hin g a8x 0 1 resistor external a5x 0 1 nonmultiplexe d ( d efault) a dd ress multiplexe d a9x 0 1 ena b le d termination disa b le d ( d efault) on-die termination on-die termination unuse d ax ay 2 v ext v dd v dd q v ref c k# c k c md 200s min t mr sc t r c 2,048 c y c les min 6 2,048 c y c les min mr s rf0 rf1 rf7 a c don ? t c are add v tt a 1 mr s ax 2 ay t mr sc nop nop nop nop
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 34 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii address mapping advance address mapping the address mapping is described in table 14 as a function of data width and burst length. notes: 1. x means ?don?t care.? 2. reserved for a20 expans ion in multiplexed mode. 3. reserved for a21 expans ion in multiplexed mode. table 14: address mapping in multiplexed address mode note 1 data width burst length ball address a0 2 a3 a4 a5 3 a8 a9 a10 a13 a14 a17 a18 x36bl = 2axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 4axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 bl = 8axa0a3a4a5a8a9a10a13a14a17x ay x a1 a2 x a6 a7 x a11 a12 a16 a15 x18bl = 2axa0a3a4a5a8a9a10a13a14a17a18 ay a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 4axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 8axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 x9bl = 2axa0a3a4a5a8a9a10a13a14a17a18 ay a20 a1 a2 a21 a6 a7 a19 a11 a12 a16 a15 bl = 4axa0a3a4a5a8a9a10a13a14a17a18 ay a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 bl = 8axa0a3a4a5a8a9a10a13a14a17a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 35 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii configuration table advance configuration table in multiplexed address mode, the read and write latencies are increased by one clock cycle. the rldram cycle time remains the same, as described in table 15. notes: 1. bl = 8 is not availabl e for configurations 1 and 4. refresh command in mu ltiplexed address mode similar to other commands, the refresh comman d is executed on the next rising clock edge when in the multiplexed address mode. however, since only bank address is required for aref, the next command can be applied on the following clock. the opera- tion of the aref command and any othe r command is represented in figure 32. figure 32: burst refresh operation note: a x : first part a x of address a y : second part a y of address ba k : bank k ; k is chosen so that t rc is met table 15: configuration table in multiplexed address mode (calculating t rc based off of clock frequency) frequency symbol configuration unit 1 1 2 3 4 1 5 6 t rc468357cycles t rl579468cycles t wl6810579cycles 533 mhz t rc 15.0 ns t rl 16.875 ns t wl 18.75 ns 400 mhz t rc 15.0 20.0 17.5 ns t rl 17.5 22.5 20.0 ns t wl 20.0 25.0 22.5 ns 300 mhz t rc 20.0 26.7 16.7 23.3 ns t rl 23.3 30.0 20.0 26.7 ns t wl 26.7 33.3 23.3 30.0 ns 200 mhz t rc 20.0 30.0 40.0 15.0 25.0 35.0 ns t rl 25.0 35.0 45.0 20.0 30.0 40.0 ns t wl 30.0 40.0 50.0 25.0 35.0 45.0 ns addr ck# ck cmd 012345678 ac aref aref aref aref aref aref aref don?t care aref 9 10 ax ay ac ax ay 11 baddr bak ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 bak
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 36 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii refresh command in multiplexed address mode advance figure 33: write burst basic sequence: bl = 4, with multiplexed addresses, configuration 1, wl = 6 figure 34: read burst basic sequence: bl = 4, with multiplexed addresses, configuration 1, rl = 5 ck# ck cmd 012 34 567 8 addr wl = 6 dq d0a d0c d0b d0d d1a d1 wr ax ba0 ay ax ba1 ay ax ba2 ay ax ba3 ay ax ba0 nop wr nop wr nop wr nop wr dkx# dkx don?t care undefined ck# ck cmd 012345678 addr rl = 5 dq qkx qkx# q0a q0c q0b q0d q1a q1b q1c rd nop rd nop rd nop rd nop rd don?t care ax ba0 ay ax ba1 ay ax ba2 ay ax ba0 ay ax ba1 qvld
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 37 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii ieee 1149.1 serial boundary scan (jtag) advance ieee 1149.1 serial boundary scan (jtag) rldram incorporates a serial boundary scan te st access port (tap). this port operates in accordance with ieee standard 1149.1-2001. the tap operates using logic levels asso- ciated with the v dd q supply. rldram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate rldram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconne cted. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state, which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input inform ation into the registers and can be connected to the input of any of the registers. the re gister between tdi and tdo is chosen by the instruction that is loaded into the tap inst ruction register. for information on loading the instruction register, see figure 35 on page 38. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any register (see figure 36 on page 38). test data-out (tdo) the tdo output ball is used to serially cloc k data-out from the registers. the output is active depending upon the current state of the tap state machine (see figure 35). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register (see figure 36).
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 38 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii test access port (tap) advance figure 35: tap controller state diagram figure 36: tap controller block diagram note: x = 112 for all configurations. performing a tap reset a reset is performed by forcing tms high (v dd q) for five rising edges of tck. this reset does not affect the operation of th e rldram and may be performed while the rldram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the rldram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. test-lo g ic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 3 4 5 6 7 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 39 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii tap instruction set advance instruction register eight-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls, as shown in figure 36 on page 38. upon power-up, the instruction regi ster is loaded with the idcode instruc- tion. it is also loaded with the idcode instru ction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the rldram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the rldram. several balls are also included in the scan register to reserved balls. the rldram has a 113-bit register. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. table 22 on page 44 shows the order in which the bits are connected. each bit corre- sponds to one of the balls on the rldram pa ckage. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-speci fic, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hard- wired into the rldram and can be shifted out when the tap controller is in the shift- dr state. the id register has a vendor code and other information described in table 19 on page 43. tap instruction set overview many different instructions (2 8 ) are possible with the 8-bit instruction register. all used combinations are listed in table 21 on page 43. these six instructions are described in detail below. the remaining instructions are reserved and should not be used. the tap controller used in this rldram is fully compliant to the 1149.1 convention. instructions are loaded into the tap contro ller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register thro ugh the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state.
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 40 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii tap instruction set advance extest the extest instruction allows circuitry extern al to the component package to be tested. boundary-scan register cells at output balls ar e used to apply a test vector, while those at input balls capture test results. typically, th e first test vector to be applied using the extest instruction will be shifted into th e boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output balls. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the in struction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruct ion is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. high-z the high-z instruction causes the boundary scan register to be connected between the tdi and tdo. this places all rldr am outputs into a high-z state. clamp when the clamp instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register. sample/preload when the sample/preload instruction is load ed into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirec- tional balls is captured in the boundary scan register. the user must be aware that the tap controll er clock can only operate at a frequency up to 50 mhz, while the rldram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar- antee as to the value that will be captur ed. repeatable results may not be possible. to ensure that the boundary scan register will capture the correct value of a signal, the rldram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time ( t cs plus t ch). the rldram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/pre- load instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens th e boundary scan path when multiple devices are connected together on a board. reserved for future use the remaining 22 instructions are not implemented but are reserved for future use. do not use these instructions.
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 41 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii tap instruction set advance figure 37: tap timing notes: 1. all voltages referenced to v ss ( g nd). 2. overshoot: v ih ( ac ) v dd + 0.7v for t t ck/2. undershoot: v il ( ac ) -0.5v for t t ck/2. during normal operation, v dd q must not exceed v dd . table 16: tap ac electrical characteristics and operating conditions +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted description symbol min max units notes input high (logic 1) voltage v ih v ref + 0.3 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.3 v 1, 2 t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don?t care undefined
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 42 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii tap instruction set advance notes: 1. t cs and t ch refer to the setup and hold time re quirements of latching data from the boundary scan register. notes: 1. all voltages referenced to v ss ( g nd). 2. overshoot: v ih ( ac ) v dd + 0.7v for t t ck/2. undershoot: v il ( ac ) -0.5v for t t ck/2. during normal operation, v dd q must not exceed v dd . table 17: tap ac electrical characteristics note 1; +0c t c +95c; +1.7v v dd +1.9v description symbol min max units clock clock cycle time t thth 20 ns clock frequency f tf 50 mhz clock hi g h time t thtl 10 ns clock low time t tlth 10 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns tdi valid to tck hi g h t dvth 5 ns tck hi g h to tdi invalid t thdx 5 ns setup times tms setup t mvth 5 ns capture setup t cs 5 ns hold times tms hold t thmx 5 ns capture hold t ch 5 ns table 18: tap dc electrical characteristics and operating conditions +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted description condition symbol min max units notes input high (logic 1) voltage v ih v ref + 0.15 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.15 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output disabled, 0v v in v dd q il o -5.0 5.0 a output low voltage i olc = 100a v ol 10.2v1 output low voltage i olt = 2ma v ol 20.4v1 output high voltage |i ohc | = 100a v oh 1v dd q - 0.2 v 1 output high voltage |i oht | = 2ma v oh 2v dd q - 0.4 v 1
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 43 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii tap instruction set advance table 19: identification register definitions instruction field all devices description revision number (31:28) abcd ab = die revision cd = 10 for x36, 01 for x18, 00 for x9. device id (27:12) 00jkidef10100111 def = 000 for 288m, 001 for 576m, 010 for 1 g . i = 0 for common i/o, 1 for separate i/o. jk = 00 for rldram, 01 for rldram ii. micron jedec id code (11:1) 00000101100 allows unique identification of rldram vendor. id register presence indicator (0) 1 indicates the presence of an id register. table 20: scan register sizes register name bit size instruction 8 bypass 1 id 32 boundary scan 113 table 21: instruction codes instruction code description extest 0000 0000 captures i/o ring contents. places the bo undary scan register between tdi and tdo. this operation does not affect rldram operations. id code 0010 0001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect rldram operations. sample/preload 0000 0101 captures i/o ring contents. places the bo undary scan register between tdi and tdo. clamp 0000 0111 selects the bypass register to be connected between tdi and tdo. data driven by output balls are determined from values held in the boundary scan register. high-z 0000 0011 selects the bypass register to be connected between tdi and tdo. all ouputs are forced into high-z state. bypass 1111 1111 places the bypass register between tdi an d tdo. this operation does not affect rldram operations.
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 44 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii tap instruction set advance notes: 1. any unused balls that are in the order will read as a logic ?0.? table 22: boundary scan (exit) order bit# bga ball bit# bga ball bit# bga ball 1k139r1177c11 2k240r1178c11 3l241p1179c10 4l142p1180c10 5m143p1081b11 6m344p1082b11 7 m2 45 n11 83 b10 8 n1 46 n11 84 b10 9 p1 47 n10 85 b3 10 n3 48 n10 86 b3 11 n3 49 p12 87 b2 12 n2 50 n12 88 b2 13 n2 51 m11 89 c3 14 p3 52 m10 90 c3 15 p3 53 m12 91 c2 16 p2 54 l12 92 c2 17 p2 55 l11 93 d3 18 r2 56 k11 94 d3 19 r3 57 k12 95 d2 20 t2 58 j12 96 d2 21 t2 59 j11 97 e2 22 t3 60 h11 98 e2 23 t3 61 h12 99 e3 24 u2 62 g 12 100 e3 25 u2 63 g 10 101 f2 26 u3 64 g 11 102 f2 27 u3 65 e12 103 f3 28 v2 66 f12 104 f3 29 u10 67 f10 105 e1 30 u10 68 f10 106 f1 31 u11 69 f11 107 g 2 32 u11 70 f11 108 g 3 33 t10 71 e10 109 g 1 34 t10 72 e10 110 h1 35 t11 73 e11 111 h2 36 t11 74 e11 112 j2 37 r10 75 d11 113 j1 38 r10 76 d10 ? ?
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 45 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii electrical characteristics advance electrical characteristics stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at thes e or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. junction temperature de pends upon package type, cycle time, loading, ambient tempera- ture, and airflow. notes: 1. all voltages referenced to v ss ( g nd). 2. typically the value of v ref is expect to be 0.5 x v dd q of the transmitting device. v ref is expected to track variations in v dd q. 3. peak-to-peak ac noise on v ref must not exceed 2% v ref (dc). 4. overshoot: v ih ( ac ) v dd + 0.7v for t t ck/2. undershoot: v il ( ac ) -0.5v for t t ck/2. during normal operation, v dd q must not exceed v dd . control input signal s may not have pulse widths less than t ck/2 or operate at frequencies exceeding t ck (max). 5. v dd q can be set to a nominal 1.5v + 0.1v or 1.8v + 0.1v supply. figure 38: absolute maximum ratings parameter min max units notes storage temperature -55 +150 c i/o voltage -0.3v v dd q + 0.3 v voltage on v ext supply relative to v ss -0.3 +2.8 v voltage on v dd supply relative to v ss -0.3 +2.1 v voltage on v dd q supply relative to v ss -0.3 +2.1 v junction temperature 110 c 1 table 23: dc electrical characteristics and operating conditions +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted description condition symbol min max units notes supply voltage v ext 2.38 2.63 v 1 supply voltage v dd 1.7 1.9 v 1, 4 dll supply v dd l1.7 v dd v4 isolated output buffer supply v dd q1.4 v dd v 1, 4, 5 reference voltage v ref 0.49 v dd q 0.51 v dd qv 1?3, 8 termination voltage v tt 0.95 v ref 1.05 v ref v9, 10 input high (logic 1) voltage v ih v ref + 0.1 v dd q + 0.3 v 1, 4 input low (logic 0) voltage v il v ss q - 0.3 v ref - 0.1 v 1, 4 output high current v oh = v dd q/2 i oh (v dd q/2) / (1.15 rq/5) (v dd q/2) / (0.85 rq/5) ma 6, 7, 11 output low current v ol = v dd q/2 i ol (v dd q/2) / (1.15 rq/5) (v dd q/2) / (0.85 rq/5) ma 6, 7, 11 clock input leakage current 0v v in v dd i lc -5 5 a input leakage current 0v v in v dd i li -5 5 a output leakage current 0v v in v dd qi lo -5 5 a reference voltage current i ref -5 5 a
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 46 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii electrical characteristics advance 6. i oh and i ol are defined as absolute values and are measured at v dd q/2. i oh flows from the device, i ol flows into the device. 7. if mrs bit a8 is 0, use rq = 250 in the equation in lieu of pr esence of an external imped- ance matched resistor. 8. v ref is expected to equal v dd q/2 of the transmitting device and to track variations in the dc level of the same. peak-to-pe ak noise (non-common mode) on v ref may not exceed 2% of the dc value. thus, from v dd q/2, v ref is allowed 2%v dd q/2 for dc error and an additional 2%v dd q/2 for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 9. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 10. on-die termination may be selected using mo de register bit 9 (see figure 8 on page 19). a resistance r tt from each data input si gnal to the nearest v tt can be enabled. r tt = 150 (10%) at +70c t c . 11. for v ol and v oh , refer to the rldrma ii hspi ce or ibis driver models. figure 39: output test conditions figure 40: input waveform table 24: ac electrical characteristics and operating conditions +0c t c +95c; +1.7v v dd +1.9v, unless otherwise noted description conditions symbol min max units input high (logic 1) voltage matched impedance mode v ih v ref + 0.2 v dd q + 0.3 v input low (logic 0) voltage matched impedance mode v il v ss q - 0.3 v ref - 0.2 v table 25: capacitance description conditions symbol min max units address/control input capacitance t a = 25c; f = 1 mhz c i 1.5 2.5 pf i/o capacitance (dq, dm, qk) c o 3.5 5.0 pf clock capacitance c ck 2.0 3.0 pf 10pf dq 50 v tt test point v ih ( ac ) min v il ( ac ) max rise time: 2 v/ns fall time: 2 v/ns v dd q g nd v swin g
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 47 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii electrical characteristics advance table 26: i dd operating conditions and maximum limits notes 1?6 on page 48 description condition symbol max units -18e -25e -25z -25 -33 -33 standby current t ck = idle all banks idle, no inputs toggling i sb 1 (v dd ) x 36 48 48 48 48 48 48 ma i sb 1 (v dd ) x 18/ x 9484848484848 i sb 1 (v ext ) 262626262626 active standby current cs# = 1 no commands, half bank/address/ data change once every four clock cycles isb2 (v dd ) x 36 288 233 233 233 189 189 ma i sb 2 (v dd ) x 18/ x 9 288 233 233 233 189 189 i sb 2 (v ext ) 262626262626 operational current bl = 2, sequential bank access, bank transitions once every t rc, half address transitions once every t rc, read followed by write sequence, continuous data during write commands i dd 1 (v dd ) x 36 374 343 343 343 292 292 ma i dd 1 (v dd ) x 18/ x 9 348 305 305 305 255 255 i dd 1 (v ext ) 413636363232 operational current bl = 4, sequential bank access, bank transitions once every t rc, half address transitions once every t rc, read followed by write sequence, continuous data during write commands i dd 2 (v dd ) x 36 418 389 389 389 339 339 ma i dd 2 (v dd ) x 18/ x 9 362 319 269 362 319 269 i dd 2 (v ext ) 484242423939 operational current bl = 8, sequential bank access, bank transitions once every t rc, half address transitions once every t rc, read followed by write sequence, continuous data during write commands i dd 3 (v dd ) x 36 454 411 411 411 347 347 ma i dd 3 (v dd ) x 18/ x 9 408 368 368 368 286 286 i dd 3 (v ext ) 554848484141 burst refresh current eight bank cyclic refresh, continuous address/data, command bus remains in refresh for all eight banks i ref 1 (v dd ) x 36 685 545 545 545 375 375 ma i ref 1 (v dd ) x 18/ x 9 680 530 530 530 367 367 i ref 1 (v ext ) 133 111 111 111 105 105 distributed refresh current single bank refresh, sequential bank access, half address transitions once every t rc, continuous data i ref 2 (v dd ) x 36 326 281 281 281 227 227 ma i ref 2 (v dd ) x 18/ x 9 325 267 367 367 221 221 i ref 2 (v ext ) 484242423939 operating burst write current example bl = 2, cyclic bank access, half of address bits change every clock cycle, continuous data, measurement is taken during continuous write i dd 2 w (v dd ) x 36 990 914 914 914 676 676 ma i dd 2 w (v dd ) x 18/ x 9 970 819 819 819 597 597 i dd 2 w (v ext ) 100 90 90 90 69 69 operating burst write current example bl = 4, cyclic bank access, half of address bits change every two clocks, continuous data, measurement is taken during continuous write i dd 4 w (v dd ) x 36 882 790 567 882 790 567 ma i dd 4 w (v dd ) x 18/ x 9 779 609 439 779 609 439 i dd 4 w (v ext ) 887777776363 operating burst write current example bl = 8, cyclic bank access, half of address bits change every four clock cycles, continuous data, measurement is taken during continuous write i dd 8 w (v dd ) x 36 737 617 617 617 461 461 ma i dd 8 w (v dd ) x 18/ x 9 668 525 525 525 364 364 i dd 8 w (v ext ) 605151514040
pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 48 ?2005 micron technology, inc. all rights reserved. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii electrical characteristics advance notes: 1. i dd specifications are tested after the de vice is properly initialized. +0c t c +95c; +1.7v v dd +1.9v, +2.38v v ext +2.63v, +1.4v v dd q +1.6v, v ref = v dd q/2. 2. t ck = t dk = min, t rc = min. 3. input slew rate is specified in table 23 on page 45. 4. definitions for i dd conditions: a. low is defined as v in v il ( ac ) max. b. hi g h is defined as v in v ih ( ac ) max. c. stable is defined as inputs remaining at a hi g h or low level. d. floating is defined as inputs at v ref = v dd q/2. e. continuous data is defined as half the dq signals changing between hi g h and low every half clock cycle (twice per clock). f. continuous address is defined as half the address signals changing between hi g h and low every clock cycle (once per clock). g. sequential bank access is defined as th e bank address incrementing by one every t rc. h. cyclic bank access is defined as the ba nk address incrementing by one for each com- mand access. for bl = 4 this is every other clock. 5. cs# is hi g h unless a read, write, aref, or mrs co mmand is registered. cs# never transi- tions more than once per clock cycle. 6. i dd parameters are specified with odt disabled. operating burst read current example bl = 2, cyclic bank access, half of address bits change every clock cycle, measurement is taken during continuous read i dd 2r (v dd ) x 36 920 850 850 850 628 628 ma i dd 2 r (v dd ) x 18/ x 9 902 761 761 761 555 555 i dd 2 r (v ext ) 100 90 90 90 69 69 operating burst read current example bl = 4, cyclic bank access, half of address bits change every two clocks, measurement is taken during continuous read i dd 4 r (v dd ) x 36 764 734 734 734 527 527 ma i dd 4 r (v dd ) x 18/ x 9 724 566 566 566 408 408 i dd 4 r (v ext ) 887777776363 operating burst read current example bl = 8, cyclic bank access, half of address bits change every four clock cycles, measurement is taken during continuous read i dd 8 r (v dd ) x 36 680 593 593 593 462 462 ma i dd 8 r (v dd ) x 18/ x 9 621 488 488 488 338 338 i dd 8 r (v ext ) 605151514040 table 26: i dd operating conditions and maximum limits (continued) notes 1?6 on page 48 description condition symbol max units -18e -25e -25z -25 -33 -33
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are tr ademarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. advance: this data sheet contains initial de scriptions of products still under development. 576mb: x36, x18, x9 2.5v v ext , 1.8v v dd , hstl, rldram ii package dimension pdf: 09005aef81fe35b2/source: 09005aef81f83d49 micron technology, inc., reserves the right to change products or specifications without notice. mt49h16m36_2.fm - rev. b 1/06 en 49 ?2005 micron technology, inc. all rights reserved. advance package dimension figure 41: 144-ball bga notes: 1. all dimensions in millimeters. ball a1 id 17.90 ctr 0.44 0.05 0.39 0.05 ball a1 ball a1 id 0.08 a a seatin g plane 10o typ 0.08 max 10.70 ctr 11.00 0.10 4.40 5.50 0.05 8.80 2.41 ctr 0.80 typ 1.00 typ 9.25 0.05 8.50 15.40 17.00 18.50 0.10 144x ? 0.45 dimensions apply to solder balls post reflow. the pre-reflow ball diameter is 0.50 on a 0.40 smd ball pad. ball a12 mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2%ag or 96.5% sn, 3%ag, 0.5% cu

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